The Renesas RZ/V2N quad-core MPU integrates an AI accelerator, achieving up to 15 TOPS of AI inference using pruning technology. Pruning reduces memory usage and increases computing efficiency by removing parts of the AI inference process. The MPU also includes an image signal processor and two MIPI CSI-2 camera interfaces for enabling endpoint vision AI.
With the RZ/V2N, the RZ/V series expands to cover markets from the low-end RZ/V2L (0.5 TOPS) to the high-end RZ/V2H (up to 80 TOPS). At just 15 mm², the RZ/V2N is significantly smaller than the high-end RZ/V2H, reducing the mounting area by 38%. It also delivers a power efficiency of 10 TOPS/W.
Along with the DRP-AI3 accelerator, the RZ/V2N features four Arm Cortex-A55 cores, a Cortex-M33 core, and an Arm Mali-C55 image signal processor (ISP). Its dual MIPI CSI-2 interfaces support two cameras, enabling double-angle image capture for improved spatial recognition, precise human motion analysis, and fall detection. A dual-camera setup can also capture images from different locations, allowing a single chip to count cars in a parking lot and recognize license plates.
The RZ/V2N microprocessor will be available from Renesas and its authorized distributors starting March 19, 2025.
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